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| july 2009 doc id 13518 rev 5 1/68 1 L9952GXP power management system ic features two 5v low-drop voltage regulators (250ma, 100ma continuous mode low stand-by current: v bat stby, 7a; , v 1 stby, 45a, (75a in cycl. sense) window watchdog and fail-safe output interrupt output wake-up logic with cyclic contact monitoring lin 2.1 compliant ( saej2602 compatible) transceiver 24 bit spi interface for mode control and diagnostic output drivers 4 high side drivers for e.g. led or hall (r dson,typ = 7 ) 1 high side driver out_hs ( r dson,typ = 1 ) 2 relay drivers ( r dson,typ = 2 ) outputs are short circuit protected 2 op amp's for current sensing in gnd return lines temperature warning and thermal shutdown applications automotive ecu? s such as door zone and body control modules. description the L9952GXP is a power management system ic containing two low drop regulators with advanced contact monitoring and additional peripheral functions. the integrated standard serial peripheral interface (spi) controls all L9952GXP operation modes and provides driver diagnostic functions. powersso-36 table 1. device summary package order codes tube tape and reel powersso-36 L9952GXP L9952GXPtr www.st.com
contents L9952GXP 2/68 doc id 13518 rev 5 contents 1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.1 voltage regulator: v1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.2 voltage regulator: v2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 power control in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.3 v1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.4 vbat standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 wake up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 wake up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 hall sensor ports: wu3,4, dig_out 3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8 cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.9 window ? watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.10 fail safe output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.11 reset ? generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.12 v1, v2 fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.13 low side driver outputs rel1, rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.14 pwm inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.15 operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.16 lin bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.17 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.17.1 dominant txd time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.17.2 short to battery time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.17.3 short to ground mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.18 wake up (from lin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.18.1 normal wake up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.18.2 wake up from short to gnd condition . . . . . . . . . . . . . . . . . . . . . . . . . . 22 L9952GXP contents doc id 13518 rev 5 3/68 2.18.3 rxd pin in v1 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.19 linpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.20 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.20.1 chip select not (csn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.20.2 serial data in (di) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.20.3 serial data out (do) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.20.4 serial clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.20.5 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 25 3.3 spi diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 high side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5 low side driver outputs rel1, rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 30 6.3 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3 power-on reset (vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4 voltage regulator v1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.5 voltage regulator v2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.6 reset generator (v1 supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.7 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 contents L9952GXP 4/68 doc id 13518 rev 5 7.8 high side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.8.1 output (out_hs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.8.2 outputs (out1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.9 relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.10 wake up inputs ( wu1..wu4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.11 wake up input (inh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.12 lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.13 operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.14 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.14.1 input: csn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.14.2 inputs: clk, di, pwm 1, pwm 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.14.3 input pwm 2 vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.14.4 di timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.14.5 do, fso, dig_out3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.14.6 do timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.14.7 csn timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8 spi control and status register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1.1 control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.1.2 control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.1.3 control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.1.4 status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.1.5 status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2 powersso-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.3 powersso-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 L9952GXP list of tables doc id 13518 rev 5 5/68 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pins definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9. thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 12. power-on reset (vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 13. voltage regulator v1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14. voltage regulator v2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 15. reset generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 16. watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. high side outputs (out_hs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18. high side outputs (out 1..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 19. relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 20. wake up inputs(wu1...wu4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 21. wake up input (inh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. lin receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 23. lin dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 24. lin transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 25. lin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 26. lin dc values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 27. operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 28. spi (input csn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 29. inputs: clk, di, pwm 1, pwm 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 30. input pwm2 vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 31. di timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 32. do, fso, digout3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 33. do timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 34. csn timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 35. spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 36. control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 37. configuration bit hsxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 38. configuration bit out_hsx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 39. configuration bit relx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 40. configuration bit on_v2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 41. configuration bit trig, go_vbat, go_v1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 42. control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 43. configuration bit wx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 44. configuration bit ux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 45. configuration bit lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 46. configuration bit txx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 47. configuration bit int_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 48. control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 49. configuration bit olt_hsx, vslock out, o_hs_rec, linpu and txd_tout. . . . . . . 59 list of tables L9952GXP 6/68 doc id 13518 rev 5 table 50. configuration bit levx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 51. configuration bit icxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 52. configuration bit lin slope, ls_ovuv and icmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 53. status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 54. configuration bit hsx_ol, hsx_oc and relx_oc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 55. configuration bit sht5v2, wux, inh, lin and cold start . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 56. status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 57. configuration bit ov, uv, tw, tsdx and vx fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 58. configuration bit stx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 59. configuration bit rx, wdx, trig, sht_gnd, sht_bat and dom_txd . . . . . . . . . . . . . 63 table 60. powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 61. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 L9952GXP list of figures doc id 13518 rev 5 7/68 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. operating modes, main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. fso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. nreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. lin master pull up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9. powersso-36 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 10. powersso-36 thermal resistance junction ambient vs. pcb copper area (v1 on) . . . . . 32 figure 11. powersso-36 thermal impedance junction ambient single pulse (v1 on) . . . . . . . . . . . . 32 figure 12. powersso-36 thermal fitting model (v1 on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 13. watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 14. watchdog, closed and open window tolerances and save trigger area . . . . . . . . . . . . . . . 39 figure 15. lin transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 16. spi - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 17. spi - edges timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 18. spi - csn low to high transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 19. spi - high to low transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 20. powersso-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 21. powersso-36 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 22. powersso-36 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 pin definitions and functions L9952GXP 8/68 doc id 13518 rev 5 1 pin definitions and functions figure 1. block diagram table 2. pins definitions and functions pin name powerss0-36 function gnd 1 ground v2 2 voltage regulator 2 output : 5 v supply for external loads e.g. ir receiver, potentiometer v1 3 voltage regulator 1 output : 5 v supply e.g. micro controller, can transceiver nreset 4 nreset output to micro controller - internal pull-up of typ. 100k ( reset state = low ) inh 5 wake-up input e.g. from can transceiver rxd 6 receiver output of the lin 2.1 transceiver di voltage regulator 1 high side spi logic window watchdog v s gnd v1 wu1 csn clk do out_hs out 1 rel1 rel2 wake up in high side low side output clamp fso voltage monitor wake up in wu2 inh v s temp prewar ning & shutdown under voltage - overvoltage - shutdown low side output clamp m v s v bat cyclic contact monitoring microcontroller can v bat lin 2.1 1) saej2602 rxd txd nreset voltage regulator 2 220nf v2 220nf v s wake u p in wake u p in wu3 wu4 high side high side high side out 2 out 3 out 4 + - lin linpu pwm1 pwm2 dig_out3 dig_out4 / interrupt + - esdlin1524bj wake u p in op2+ op2- op2o ut op1+ op1- op1o ut for detailed information see emc test report from ibee zwickau c (a dc) can lin r 1) lin 2.1 certified e. g. bul b, led, hall sensor e. g. led, hall sensor fail-safe logic c r c L9952GXP pin definitions and functions doc id 13518 rev 5 9/68 txd 7 transmitter input of the lin 2.1 transceiver op2+ 8 non inverting input of operational sense amplifier op2- 9 inverting input of operational sense amplifier op2 out 10 output of operational sense amplifier di 11 spi : serial data input do 12 spi : serial data output clk 13 spi : serial clock input csn 14 spi : chip select not input pwm1 15 pulse width modulation input pwm2 16 pulse width modulation input dig_out3 17 digital output dig_out4/int 18 digital output (con figurable as interrupt output) wu 4..1 19 to 22 wake-up input: input pins for static or cyclic monitoring of external contacts op1 out 23 output of operational sense amplifier op1- 24 inverting input of operational sense amplifier op1+ 25 non inverting input of operational sense amplifier out 4..1 26 to 29 high side driver (7 , typ.) - to supply e.g. led? s, hall sensors or external contacts out_hs 30 high side drivers (1 , typ.) - to supply e.g. led? s, bulbs, hall sensors or external contacts vs 31 power supply voltage linpu 32 lin master pull up lin 33 lin bus line rel1 34 low side driver (2 , typ.) - e.g. relay rel2 35 low side driver (2 , typ.) - e.g. relay fso 36 fail safe output - used to supervise or control applications in case of watchdog and/or v1 under-voltage failure (e.g. to activate emergency lights) table 2. pins definitions and functions (continued) pin name powerss0-36 function pin definitions and functions L9952GXP 10/68 doc id 13518 rev 5 figure 2. pins configuration dig _ out 3 out 4 / 2 out _ hs gnd 1 v 22 v1 3 4 5 op 2+ 6 op 2 - 7 8 di 9 do 10 clk 11 csn 12 pwm 1 13 pwm 2 14 rxd 15 txd 16 17 18 fso 36 vs 35 rel 1 34 rel 2 33 32 out 3 31 out 1 30 29 out 4 28 op 1 + 27 op 1 - 26 opout 1 25 wu 1 24 wu 2 23 wu 3 22 wu 4 21 linpu 20 lin 19 out 2 powersso - 36 l9952 gxp inh nreset opout dig int _ ta b = g n d L9952GXP description doc id 13518 rev 5 11/68 2 description 2.1 voltage regulator the L9952GXP contains 2 independent and fully protected low drop voltage regulators, which are designed for very fast transient response. the output voltage is stab le with loads capacitors > 220nf. 2.1.1 voltage regulator: v1 the voltage regulator v1 provides 5v supply voltage and up to 250ma continuous load current for the external digital logic (micro controller, can transceiver ...). in addition the regulator v1 drives the L9952GXP internal 5v loads. the voltage regulator is protected against overload and over-temperature. an external reverse current protection has to be provided by the application circuitry to prevent the output capacitor from being discharged by negative transients or low input voltage. the output voltage precision is better than +/-2% (incl. temperature drift and line-/load regulation) for operating mode; respectively +/-3% during low current mode. current limitation of the regulator ensures fast charge of external bypass capacitors. the output voltage is stable for ceramic load capacitors > 220nf. if device temperature exceeds tsd1 threshol d, all outputs (hsx, lsx, v2, lin) will be deactivated except v1. hence the micro controlle r has the possibility for interaction or error logging. in case of e xceeding tsd2 threshold (tsd2>tsd1), also v1 will be deactivated (see state chart fig. 3.1: ?protection and diagnosis?). a timer is started and the voltage regulator is deactivated for t tsd = 1sec. during this time, all other wakeup sources (can, lin, and wu1...4) are disabl ed. after 1 sec, th e voltage regulator will try to restart automatically. if tsd2 occurs within one minute and for 8 consecutive times, the L9952GXP enters the v bat - standby mode. in case of short to gnd at ?v1? after initial turn on (v1 < 2v for at least 4ms) the L9952GXP enters the v bat - standby mode. reactivation (wake-up) of the device can be achieved with signals from can, lin, wu1..4, spi. 2.1.2 voltage regulator: v2 the voltage regulator v2 supplies additional 5v loads (e.g. logic components, external sensors, external potentiometers). the continuous load current is 50ma. the regulator provides accuracy better than + 3% @ 50ma (4% @ 100ma) load current. in case of short to gnd at ?v2? after initial turn on (v2 < 2v for at least 4ms) the v2 regulator is switched off. micro processor has to send a clear command to reactivate the v2 regulator. v2 is protected against: overload over temperature short circuit (short to ground and battery supply voltage) reverse biasing description L9952GXP 12/68 doc id 13518 rev 5 2.2 power control in operating modes the L9952GXP can be operated in 4 different operating modes: active flash v 1 - standby v bat - standby a cyclic monitoring of wake-up inpu ts is available in stand-by modes. 2.2.1 active mode all functions are available. 2.2.2 flash mode to disable the watchdog feature a flash program mode is available. the mode can be entered by v pwm2 9v in this case all other functions are the same as in active mode watchdog can be disabled as well as soon as L9952GXP enters the v1 standby mode (see section 2.9 for details) note: ?high? level for flash mode selection is v pwm2 9v. for all other operation modes, standard 5v logic signals are required. for proper operation pwm 1 must not be set to a voltage level above standard 5v logic. 2.2.3 v 1 standby mode outputs and internal loads are switched off. to supply the micro controller in a low power mode, the voltage regulator1 (v1) remains active. the intention of the v1 standby mode is to preserve the ram contents. a cyclic contact supply and wake-up input sense feature (for cyclic monitoring of external contacts) can be activated by spi. 2.2.4 v bat standby mode to achieve minimum current consumption during v bat standby mode, all L9952GXP functions (except the ones for wake up functionality) are switched off. in v bat - standby mode the current consumption of the L9952GXP is reduced to 7a, typical (without cyclic sense feature selected). the transitions from active mode to either v 1 -standby or v bat - standby are controlled by spi. v bat - standby mode is dominant; i.e. if both bits, v 1 - standby and v bat - standby are set to ?1?, the l9952g xp will enter v bat - standby mode. L9952GXP description doc id 13518 rev 5 13/68 2.3 wake up events a wake-up from standby mode will switch the devi ce to active mode. this can be initiated by one or more of the following sources: change of the lin state at lin bus interfaces a current at the inh pin (i 200ua) controlled by the can-transceiver (the can transceiver is not a part of the ic). positive/negative edge at wake up pins wu1...wu4 -> change of level after going into stand-by change of open-load state at out1 to 4 spi access in v1-standby mode (csn is low and first rising edge on clk) all wake-up events (except wake-up by lin, inh or spi from v1standby mode) generate a reset pulse (nreset low for 2ms). wake-up events from v1standby by lin, inh or spi do not cause a reset and the reset generation is blocked for 2ms, i. e. a watchd og failure during this timeframe will not cause a reset. table 3. wake up events wake up source description lin always active inh always active wu1...4 can be individually disabled via spi open load at hs outputs can be individually disabled via spi spi access always active (except in v bat - standby mode) high level at pwm2 input vpwm2 > 9v (1) 1. only if internal oscillator is running (e. g. in cyclic sense confi guration or after wake-up request). description L9952GXP 14/68 doc id 13518 rev 5 2.4 functional over view (truth table) table 4. functional overview (truth table) function comments operating modes active mode v 1 -standby static mode (cyclic sense) v bat -standby static mode (cyclic sense) 2.3.1 voltage-regulator, v1 vout= 5v on on (1) 1. supply the processor in low current mode off 2.3.2 voltage-regulator, v2 vout= 5v on / off (2) 2. only active when selected via spi on (2) / off on (2) / off 2.3.3 reset-generator on on off 2.3.4 window watchdog v 1 monitor on off if (i_v1 < i cmp and i cmp =0) or i cmp = 1 off 2.3.5 wake up off (3) 3. input status can be read by spi (status register 0) ; inputs should be configured for static sense (control register 2) active (4) active (4) 4. unless disabled by spi 2.3.6 hs-cyclic supply oscillator timebase on / off on (2) / off on (2) / off 2.3.7 relay driver on off off 2.3.8 operational amplifiers on off off 2.3.9 lin line driver lin 2.1 on off off 2.3.10 lin line receiver on on on 2.3.11 fso fail-safe output hi ? no error lo ? wd or v1 fail hi ? no error lo ? wd or v1 fail (5) 5. watchdog is active in v1 standby mode, until i(v1) is below i cmp current threshold lo -> because v1= off 2.3.12 oscillator on (6) 6. activation = on if cyclic sense is selected (6) 2.3.13 vs-monitor on (7) 7. cyclic activation = puls ed on during cyclic sense (7) L9952GXP description doc id 13518 rev 5 15/68 figure 3. operating modes, main states active mode v1: on reset generator: active watchdog: active fail safe out: active v1 stan d b y mode v1: on reset generator: active watchdog: off (if iv1 vpor thermal shutdown tsd2 or iv1 > 1ma and icmp = 0 and 15 x wd fail flash mode watchdog: off vpwm2>9v note 1 vpwm2>9v vpwm2<7v vpwm2>9v note 1 spi command: ?go vbat? (d20 cr0) or thermal shutdown or v1 fail (v1 < 2,5v for 4ms after por) => short to gnd or 15 x wd failure note 1 : only if internal oscillator is running description L9952GXP 16/68 doc id 13518 rev 5 2.5 wake up inputs the de-bounced digital inputs wu1...wu4 can be used to wake up the L9952GXP from standby modes. these inputs are sensitive to any level transition (positive and negative edge) for static contact monitoring, a filter time of 64 s is implemented at wu1-4. the filter is started when the input voltage passes the specified threshold. at vin > 1v and vin < (vs ? 2v), a wake-up request is processed. during wake-up request, the in ternal oscillator and other circuit blocks are activated in order to allow more accurate monitoring of the inputs. in addition to the continuous sensing (static contact monitoring) at the wake up inputs, a cyclic wake up feature is implemented. this feature allows periodical activation of the wake- up inputs to read the status of the external contacts. the periodical activation can be linked to timer 1 (0.5sec to 4.0sec in 0.5sec steps) or timer 2 (50ms). the input signal is filtered with a filter time of 16us after a programmab le delay (80us or 800us). a wake-up will be processed if the status has changed versus the previous cycle. the outputs out_hs and out1-4 can be used to supply the external contacts with the timing according to the cyclic monitoring of the wake-up inputs. if the wake-up inputs are configured for cyclic sense mode (icxx in control register 2), the same input filter timing (timer1 or timer2) and the corresponding input filter delay (control register 2) must be used for the hs outputs (hsxx in control register 0) which supply the external contact switches. in standby mode, the inputs wu1-4 are spi configurable for pull-up or pull-down current source configuration according to the setup of the external contacts (pull-up for active low contacts, pull-down for active high contacts). in active mode the inputs have a pull down resistor of 100 kohm (typ). in active mode, the input status can be read by spi (status register 0). static sense should be configured (control register 2) before the read operation is started (in cyclic sense configuration, the input status is updated acco rding to the cyclic sense timing; therefore, reading the input status in this mode may not reflect the actual status). 2.6 hall sensor ports: wu3,4, dig_out 3,4 applications like hall sensor outputs need high processing speed. the 12v signals connected to the wakeup inputs wu3 and wu4 can be looped through to the digital outputs dig_out 3 and dig_out 4 (5v) in order to avoid read out of the input state by spi. the setup is programmable by spi. the open load states of the high side drivers out1 and out2 can be looped through the digital outputs dig_out3 and dig_out4 without delay. in addition, the status of out1 and out2 can be accessed through the spi interface. this feature is intended for 2-pin hall sensors. open load information is only valid during on state. the open load threshold at pins out1...4 can be switched from i old1 = 2ma to i old2 = 8 ma via spi . L9952GXP description doc id 13518 rev 5 17/68 2.7 interrupt dig_out4 can be configured via spi as interrupt output (int) by setting bit 20 / cr1:int_enable=?1?. this configuration will enab le the following behaviour: int pin is pulled high for 2ms in case of any wake-up from v1 standby mode (wu inputs, lin, inh, spi, open load hs, iv1 > i cmp _ris) wake-up events from v1 standby do not generate a reset (i.e. nreset is not pulled low) the dig_out4 settings in cr1 (bits 12..14) will be ignored 2.8 cyclic contact supply in v1 and v bat - standby mode, any high side driver output (out1..4, ouths) can be used to periodically supply external contacts. the timing is selectable by spi timer 1: period is x sec, the on-time is 10ms resp. 20ms with x {0.5, 1.0, 1.5, ... 4 } timer 2: period is 50ms, the on- time is 100us resp. 1ms: note: cyclic sense setup : if cyclic sense feature is used for wake-up inputs (icxx in control register 2), same input filter timing (t imer1 or timer2) must be used for hs outputs (hsxx in control register 0). 2.9 window ? watchdog during normal operation the watchdog monitors the micro controller within a nominal trigger cycle of 10ms. in v bat -standby , v1-standby and flash program modes, the watchdog circuit is automatically disabled. however, the watch dog will remain enabled in v1-standby mode until the current at v1 decreases below i cmp _fall. the v1 current monitoring can be disabled, if the i cmp bit (cr2, d20) is set to '1'. after ?power-on?, ?standby mode? or reset, the window watchdog starts with a long open window (65ms). the long open window allows the micro controller to run its own setup and then to trigger the watchdog via the spi. the trigger is finally accepted when the csn input becomes high after the transmission of the spi word. a correct watchdog trigger will start the window watchdog with a closed window (< 6ms) followed by an open window (< 10ms), see timing diagrams. subsequently, the micro controller has to serve the watchdog by alternating the watchdog trigger bit (cr0, d19). the ?negative? or ?positive? edge has to meet the open window time. a correct watchdog trigger signal will immediately start the next closed window. after 8 watchdog failures in sequence, the v1 regulator is switched off for 200ms. in case of 7 further watchdog failures, the v1 regulator is completely turned off and the device goes into v bat - standby mode until a wakeup occurs. (e.g. via lin, can/inh). description L9952GXP 18/68 doc id 13518 rev 5 the watchdog is triggered by toggling the trigger bit (cr0, d19). note: the active trigger window will be reset after each correct trig ger write operation. in case of reset (nreset low for 2ms) the trigger bit is set to ?0?. in case of a wd failure, the outputs (lsx, hsx, v2) are switched off and nreset is pulled low for 2ms. writing to control register 0 without inverting the wd trigger bit is possible at any time. figure 4. watchdog watchdog active with normal window (10ms) hsd, lsd : according to cr0 reset (nreset =low for 2ms) lsd: off (control bits set to ? 0') hsd: off (control bits remain unchanged ) watchdog active with ?long open window? (65ms nom ) hs and ls outputs are off watchdog inactive (standby modes , flash mode) watchdog failure (?long open window? passed without trig=1 2ms set wd trigger bit = ? 1' or toggle trigger bit if wake-up from v1standby set wd trigger bit = ?0' or write non-inverting value to trigger bit after wake-up from v1standby mode go to standby mode or flash mode (pwm2>9v) go to standby mode or flash mode (pwm2>9v) power-on reset toggle wd trigger bit within nominal window wake-up event or exit flash mode v1 off for 200 ms 8x wd failure watchdog failure vbatstdby mode 8+7 wd failures wake up event t=200ms inh, lin, spi i(v1)>1ma and icmp=0 L9952GXP description doc id 13518 rev 5 19/68 2.10 fail safe output after power-on (vs > v por ) or wakeup from v bat -standby mode, the output fso is set to ?high?, if v1 is above the v1 threshold. fso is set to ?low? in case of v1 under voltage or watchdog failure. during v1-standby mode, fso is high unless a v1 under-voltage or watchdog reset occurs. wd remains enabled in v1 standby mode until i v1 drops below 150ua. in v bat - standby mode, fso is low. at exit from v bat - standby mode, it goes to high as soon as v1 is stable. at wakeup fso remains high, provided that the watchdog is triggered successfully. it is set low if the watchdog is not served during the long open window of if a v1 under-voltage occurs. figure 5. fso 2.11 reset ? generator if v1 is turned on and the voltage exceeds the v1 reset threshold, the reset output ?nreset? is switched to ?high? after a 2ms reset delay time. this is necessary for a defined start of the micro controller when the application is switched on. as soon as an under voltage condition of the output voltage (v1 < vrt) for more than 8us appears, the reset output is switched low again. figure 6. nreset fso = 0 vbatstdby mode v1 undervoltage watchdog failure tsd2 nreset = 0 v1 undervoltage wake-up event 1) 1) only if (int_en = 0) and (wake-up by wu-input or high side open load) vpwm2 < 9v (exit flash mode) watchdog failure description L9952GXP 20/68 doc id 13518 rev 5 2.12 v1, v2 fail the v 1, and v 2 regulator output voltages are monitored. in case of a drop below the v 1, v 2 ? fail thresholds (v 1,2 < 2v,typ for t > 2us), the v 1,2 - fail bits are latched. the fail bits are cleared by a dedicated spi command. if 4ms after turn on of the regulator the v 1,2 voltage is below the v 1,2 fail thresholds, (independent for v1,2 ), the L9952GXP will identify a short circuit condition at the related regulator output and the regu lator will be switched off. in case of a v1 failure the device enters v bat - standby mode automatically. in case of a v2 failure the sht5v2 bit (sr0 bit12) is set. 2.13 low side driver outputs rel1, rel2 the outputs rel1, rel2 (r dson = 2 typ. @25 c) are specially designed to drive relay loads. typical relays used have the following characteristics: relay type 1: ? closed armature: r = 160 + 10%, l= 300mh ? open armature: r = 160 + 10%, l= 240mh relay type 2: ? closed armature: r= 220 + 10%, l= 420mh ? open armature: r= 220 + 10%, l= 330mh the outputs provide an active output zener clamping (40v) feature for the demagnetisation of the relay coil, even though a load dump condition exists. in case of watchdog failure the relay drivers will be switched off and the low side driver control bits are cleared. note: 1 due to relays bouncing, high dv/dt and/or di/dt transients may occur on the low side driver outputs. in case high currents are switched (for example window lift motor), due to parasitic capacitive inductive coupling from load side of relays to the relays coils, the absolute maximum ratings of the low side driver outputs may be exceeded. in order to avoid this, it is recommended to place a 10nf capacitor at the rel1, rel2 outputs to gnd. 2 if a hard short circuit to v bat is possible at the "low side driver" outputs, an rc network is required with t rc > 1s, r 1 (see block diagram, the value is given for an output short circuit of given di/dt = 5a/s). 2.14 pwm inputs the inputs pwm 1,2 can be used to control the output drivers out1..4 and out_hs with a pwm signal. each pwm input can be mapped individually to each of the above listed outputs according to the spi settings. L9952GXP description doc id 13518 rev 5 21/68 2.15 operational amplifiers the operational amplifiers are especially designed to be used for sensing and amplifying the voltage drop across ground connected shunt resistors. therefore the input common mode range includes - 0.2 ... 3v. the operational amplifiers are designed for gnd + 3v... gnd ? 0.2v input voltage swing and rail-to-rail output voltage range. all pins (positive, negative and outputs ) are available to be able to operate in non-inverting and inverting mode. both operational amplifiers are on-chip compensated for stability over the wh ole operating range wit hin the defined load impedance. figure 7. lin master pull up a dedicated built-in switch ?tsw? enables the lin to act as a master. (see chapter 2.18) 2.16 lin bus interface general requirements: speed communication up to 20kbit/s lin 2.0 compliant (saej2602 compatible) transceiver function range from +40v to -18v dc at lin pin gnd disconnection fail safe at module level off mode: does not disturb network gnd shift operation at system level microcontroller interface with cmos compatible i/o pins. pull up resistor internal. esd: immunity against automotive transi ents per iso7637 specification (see application note) matched output slopes and propagation delay in order to further reduce the current consumption in standby mode, the integrated lin bus interface offers an ultra low current consumption. control vs lin control 30k lin gnd 1k master node pu ll up lin pu t sw description L9952GXP 22/68 doc id 13518 rev 5 2.17 error handling the L9952GXP provides the following 3 error handling features which are not described in the lin spec. v2.1, but are realized in different stand alone lin transceivers / micro controllers to switch the application back to normal operation mode. 2.17.1 dominant txd time out if txi is in dominant state (low ) for more than 12ms (typ) the tr ansmitter will be disabled until txi becomes recessive (high). this feature can be disabled via spi. 2.17.2 short to battery time out if txi changes to dominant (low) state but rxi signal does not follow within 40 s, the transmitter will be disabled unt il txi becomes recessive (high). 2.17.3 short to ground mode a wake up caused by a message on the bus will start the voltage regulator and the micro controller to switch the application back to normal operation mode. 2.18 wake up (from lin) in standby mode the L9952GXP can receive a wake up from lin bus. for the wake up feature the L9952GXP logic differentiates two different conditions. 2.18.1 normal wake up normal wake up can occur when the lin transceiver was set in standby mode while lin was in recessive (high) state. a do minant level at lin for at leas t 40s, will switch the L9952GXP to active mode. 2.18.2 wake up from s hort to gnd condition if the lin transceiver was set in standby mode while lin was in dominant (low) state, recessive level at lin for at least 40us, will switch the L9952GXP to active mode. 2.18.3 rxd pin in v1 standby in v1 standby condition the rxd is a tristate pin. L9952GXP description doc id 13518 rev 5 23/68 2.19 linpu the linpu (lin pull up) signal is set by L9952GXP logic in order to drive the lin transceiver in master mode. the master mode is realized by an internal high side switch and an external diode in series with an external 1k resistor. in master mode the high side switch is closed causing an external pull up path in parallel to the internal one (diode & 30k resistor). hs (high side) characteristics: hs does not have an over current protection. the hs remains active in standby mode. switch off only in case of over temperature (tsd2 = thermal shutdown #2). typical r dson , 10 . the linpu is activated by default (lin master mode) and can be switched off with a spi command (see register 2) to reduce current in case of lin shorted to ground. 2.20 serial peripheral interface (spi) a 24 bit spi command (2 adresses + 22 data bits) is used for bi-directional communication with the micro controller. during active mode, the spi: 1) triggers the watchdog 2) controls the modes and status of all L9952GXP modules (incl. input and output drivers) 3) provides driver output diagnostic 4) provide l9952 diagnostic (incl. over temperature warning, L9952GXP operation status) note: during stand-by modes, the spi is generally deactivated. the spi can be driven by a micro controller with its spi peripheral running in following mode: cpol=0 and cpha=0. for this mode input data is sampled by the low to high transition of the clock clk, and output data is changed from the high to low transition of clk. this device is not limited to micro cont roller with a build-in spi. only three cmos- compatible output pins and one input pin will be needed to communicate with the device. a fault condition can be detected by setting csn to low. if csn = 0, the do-pin will reflect the global error flag (fault condition) of the device which is a logical -?or? of all over current, vs- over / under voltage, temperature warning/shutdown and v1 fail bits. the micro controller can poll the status of the device without the need of a full spi-communication cycle. 2.20.1 chip select not (csn) the input pin is used to select the serial interface of this device. when csn is high, the output pin (do) will be in high impedance state. a low signal activates the output driver and a serial communication can be started. the state during csn = 0 is called a communication frame. description L9952GXP 24/68 doc id 13518 rev 5 2.20.2 serial data in (di) the input pin is used to transfer data serial in to the device. the data applied to the di will be sampled at the rising edge of the clk signal and shifted into an internal 24 bit shift register. at the rising edge of the csn si gnal the contents of the shift register will be transferred to data input register. the writing to the selected data input register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. csn low). if more or less clock pulses are counted within one frame the complete frame will be ignored. this safety function is implemented to avoid an activation of the output stages by a wrong communication frame. note: due to this safety functionality a daisy chai ning of spi is not possible. instead, a parallel operation of the spi bus by controlling th e csn signal of the connected ic's is recommended. 2.20.3 serial data out (do) the data output driver is activated by a logi cal low level at the csn input and will go from high impedance to a low or high level depending on the global error flag (fault condition). the first rising edge of the clk input after a high to low transition of the csn pin will transfer the content of the selected status register into the data out shift register. each subsequent falling edge of the clk will shift the next bit out. 2.20.4 serial clock (clk) the clk input is used to synchronize the input and output serial bit streams. the data input (di) is sampled at the rising e dge of the clk and the data ou tput (do) will ch ange with the falling edge of the clk signal. the spi can be driven with a clk frequency up to 1mhz. 2.20.5 data registers the device has 3 control registers and 2 status registers. the first two bits (d22+d23) at the di-input are used to select one of the control registers. all bits are first shifted into an input shift register. after the rising edge of csn the contents of the input shift register will be written to the selected control register only if a frame of exact 24 bits is detected. if the control register 1 is selected fo r data transfer, the status regi ster 1 will be transferred to the do during the current communication frame. for the selection of control register 0 or control register 2, the status register 0 is transferred to do. L9952GXP protection and diagnosis doc id 13518 rev 5 25/68 3 protection and diagnosis 3.1 power supply fail over and under-voltage detection on vs. 3.1.1 over voltage if the supply voltage vs reaches the over voltage threshold (v sov ) the outputs hs1..4, out_hs, rel1,2, and lin are switched to high impedance state (load protection) the over voltage bit is set and can be cleared with the clear bit (cr1,clr) automatic recovery after vs over-voltage; selectable via spi (cr2, bit4) 3.1.2 under voltage if the supply voltage vs drops below the under voltage threshold voltage(v suv ) the outputs hs1..4, ouths, rel1,2, and lin are switched to high impedance state (load protection) the under voltage bit is set automatic recovery after vs under-voltage; selectable via spi (cr2, bit4) 3.2 temperature warnin g and thermal shutdown see state chart: ? protection and diagnosis?. 3.3 spi diagnosis digital diagnosis features are provided by spi: v1 reset threshold programmable over temperature including pre warning open load separately for each output stage overload status vs-supply over/under voltage v1 and v2 fail bit status of the wu1...4, lin and inh pin cold start bit number of unsuccessful v1 restarts after thermal shutdown number of sequential watchdog failures status of watchdog trigger bit trig: (sr1, bit 16) lin status (short to ground, short to v bat , dominant txd) see the following state chart: ?protection and diagnosis?. protection and diagnosis L9952GXP 26/68 doc id 13518 rev 5 figure 8. protection and diagnosis active mode standby modes (during cyclic sense ) vs lockout all outputs: off uv bit set (d1 sr1) auto-restart if selected by spi vs lockout all outputs: high impedance ov bit set (d0 sr1) auto-restart if selected by spi vs overvoltage temperature warning ?temper ature war ning'- bit set (d2 sr1) tsd1 all outputs except v 1: off ?t sd 1'-bit is set ( d 3 sr1) tj > 140c spi command: ?clr? (d21 cr1) or power-on reset tsd2 all outputs: off v1: off for 1 sec ?tsd2-bit is set (d4 sr1) tj > 155c vbatstdby all outputs incl v 2: off 8x tsd2 (each tsd2 within 1 min) spi command: ?clr? (d21 cr1) or autorestart activated (d4 cr2) spi command: ?clr? (d21 cr1) or autorestart activated (d4 cr2) vs undervoltage wake-up event power-on reset spi command: ?clr? (d21 cr1) or power-on reset tj > 130c v1 off for 200ms 8 successive watchdog failures 7 additional watchdog failures in sequence vbatstdby mode t > 1 s e c L9952GXP protection and diagnosis doc id 13518 rev 5 27/68 3.4 high side driver outputs the component provides a total of 4 high side outputs out1...4, (7 typ. @ 25c) to drive e.g. led' s or hall sensors and 1 high side output out_hs with 1 typ. @ 25 c). the high side outputs are protected against over- and under voltage overload (short circuit) over temperature with pre warning if the output current exceeds the current shutdown threshold the output transistor is turned off and the corresponding diagnosis bit of the output is set. the switches are automatically disabled in case of reset condition, vs-under, vs-over voltage or thermal shutdown (tsd1&2). for out_hs an auto recovery feature is available in active mode. if the out_hs output current exceeds the current shutdown threshold, the output transistor is turned off and the corresponding diagnosis bit of the output is set. via spi command the auto recovery feature can be enabled in order to restart the driver in case of over current shutdown. this over current recovery feature is intended for loads which have an initial current higher than the over current limit of the output (e.g. inrush current of cold light bulbs). the device itself can not distinguish between a real overload and a non linear load like a light bulb. a real overload condition can only be qualified by time. as an example, the micro controller can switch on light bulbs by setting the over current recovery bit for the first 50ms. after clearing the recovery bit, the output will be automatically disabl ed if the overload condition still exists. the status of all high side outputs (over-current, open load) can be monitored by spi interface. in case of a watchdog failure, the high side drivers are switched off. the control bits are not cleared, i.e. the drivers will go to the previous state once the watchdog failure condition disappears. esd structures are configured for nominal currents only. if external loads are connected to different grounds, the current load must be limited to this nominal current. note: loss of ground or ground shift with externally grounded loads. 3.5 low side driver outputs rel1, rel2 the outputs provide an active output zener clamping feature for the demagnetisation of the relay coil, even though a load dump conditi on exists. for safety reasons the relay drivers are linked with the watchdog: in case of failure , or missing trigger sign al the relay drivers will switch off. absolute maximum ratings L9952GXP 28/68 doc id 13518 rev 5 4 absolute maximum ratings note: all maximum ratings are absolute ratings. leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit ! table 5. absolute maximum ratings symbol parameter value unit v s dc supply voltage / ?jump start? -0.3 to +28 v single pulse / t max < 400 ms ?transient load dump? -0.3 to +40 v v 1 stabilized supply voltage, logic supply -0.3 to +5.25 v v 2 stabilized supply voltage -0.3 to +28 v v di v clk v txd v csn v do v rxd v nreset v fso v digout3,4 logic input / output voltage range -0.3 to v1+0.3 v v inh v pwm1, v pwm2, v rel1, v rel2, wake up input voltage range pwm input voltage range low side output voltage range -0.3 to +40 v v out1..4,, v outh high side output voltage range -0.3 to v s + 0.3 v v wu1...4, wake up input voltage range -0.3 to v s + 0.3 v v op1+, v op1-, v op2+, v op2-, opamp1 input voltage range opamp2 input voltage range -0.3 to v1 + 0.3 v v opout1, v opout2 analog output voltage range -0.3 to v s + 0.3 v v lin, v linpu lin bus i/o voltage range -20 to +40 v i input current injection into vs related input pins 5ma L9952GXP esd protection doc id 13518 rev 5 29/68 5 esd protection table 6. esd protection parameter value unit all pins, except lin (1) 1. hbm (human body model, 100pf, 1.5 k ) according to mil 883c, method 3015.7 or eia/jesd22a114-a +/- 2 kv all output pins (2) 2. hbm with all none zapped pins grounded +/- 4 kv lin (3) 3. without external components +/- 1.5 kv lin (4) 4. acc. din en61000-4-2 (330 , 150 pf), with external components: - diode, type esdlin1524bj - smd ferrite bead, type tdkmmz2012y202b - capacitor c=220pf for detailed information please see emc report from ibee zwickau (available on request) +/- 8 kv all pins (charge device model) +/- 500 v corner pins (charge device model) +/- 750 v all pins (5) 5. acc. machine model: c=220pf; l=0.75h; r=10 +/- 200 v thermal data L9952GXP 30/68 doc id 13518 rev 5 6 thermal data 6.1 operating junction temperature 6.2 temperature warnin g and thermal shutdown table 7. operating junction temperature item symbol para meter value unit 6.1.1 tj operating junction temperature - 40 to 150 c 6.1.2 rthja thermal resist ance junction- ambient see figure 10. c/w table 8. temperature warning and thermal shutdown item symbol parameter min. typ. max. unit 6.2.1 t w on thermal over temperature warning threshold t j (1) 1. non-overlapping 120 130 140 c 6.2.2 t sd1 off thermal shutdown junction temperature 1 t j (1) 130 140 150 c 6.2.3 t sd2off thermal shutdown junction temperature 2 t j (1) 140 155 170 c 6.2.4 t sd2 on hysteresis 5 c 6.2.5 t sd12hys L9952GXP thermal data doc id 13518 rev 5 31/68 6.3 package and pcb thermal data figure 9. powersso-36 pc board note: layout condition of r th and z th measurements ( board finish thickness 1.6 mm +/- 10% board double layer, board dimension 129x60, board material fr4, cu thickness 0.070mm (front and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, cu thickness on vias 0.025 mm ). thermal data L9952GXP 32/68 doc id 13518 rev 5 figure 10. powersso-36 thermal resistance junction ambient vs. pcb copper area (v1 on) figure 11. powersso-36 thermal impedance junction ambient single pulse (v1 on) 30 50 70 90 110 0246810 rthj_amb(c/ w) pcb cu heatsink area (cm^ 2) 0,1 1 10 100 1000 0,01 0,1 1 10 100 1000 time ( s) zth (c/ w) footprint 8 cm 2 2 cm 2 L9952GXP thermal data doc id 13518 rev 5 33/68 equation 1: pulse calculation formula where = t p /t figure 12. powersso-36 thermal fitting model (v1 on) table 9. thermal parameters area/island (cm 2 )footprint28 r1 (c/w) 5 r2 (c/w) 18 10 10 r3 (c/w) 29 22 7,8 r4 (c/w) 51 29 21 c1 (w.s/c) 0,0003 c2 (w.s/c) 0,35 1 1 c3 (w.s/c) 1,5 1,3 1,3 c4 (w.s/c) 5 15 15 z th r th z thtp 1 ? () + ? = electrical characteristics L9952GXP 34/68 doc id 13518 rev 5 7 electrical characteristics 7.1 supply and supply monitoring the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; 4.8v < v1 < 5.2v; all outputs open; t j = -40c...130c, unless otherwise specified. table 10. supply and supply monitoring item symbol parameter test condition min. typ. max. unit 7.1.1 v s supply voltage range 6 13.5 18 v 7.1.2 v suv vs uv-threshold voltage v s increasing / decreasing 5.11 5.81 v 7.1.3 v hyst_uv undervoltage hysteresis 0.04 0.1 0.15 v 7.1.4 v sov vs ov-threshold voltage v s increasing / decreasing 18 22 v 7.1.5 v hyst_ov overvoltage hysteresis hysteresis 0.5 1 1.5 v 7.1.6 i v(act) current concumption in active mode vs=12v, txd lin high, v2 on, outputs off iv1=iv2=0a 2.7 20 ma 7.1.7 i v(bat) current consumption in v bat - standby mode v s =12v, both voltage regulators deactivated, no wake-up request 1 7 10 a 7.1.8 i v(bat)cs current consumption in v bat - standby mode v s =12v, both voltage regulators deactivated, (cyclic sense) 40 75 100 a 7.1.9 i v(v1) current consumption in v 1 -standby mode v1=5v, v s =12v, voltage regulator v1 active, without cyclic sense, no wake-up request 10 45 70 a 7.1.10 i v(batwu) current consumption in v bat -standby mode with a pending wake up request 1.5v electrical characteristics L9952GXP 36/68 doc id 13518 rev 5 7.5 voltage regulator v2 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 5.25v < v s < 27v; t j = -40c...130c, unless otherwise specified. 7.4.7 iccmax1 short circuit output current current limitation 400 600 950 ma 7.4.8 cload1 load capacitor1 ceramic (1) 0.22 f 7.4.9 ttsd v1 deactivation time after thermal shutdown 1 s 7.4.10 i cmp_ris current comp. rising threshold rising current 0.9 2.5 4 ma 7.4.11 i cmp_fal current comp. falling threshold falling current tj= -40c...130c tj= 25c...130c 0.75 0.85 1.95 1.95 ma 7.4.12 i cmp _hys current comp. hysteresis 0.5 ma 7.4.13 v1fail v1 fail threshold v1 forced 2 v 1. placement close to the pad table 13. voltage regulator v1 (continued) item symbol parameter test condition min. typ. max. unit table 14. voltage regulator v2 item symbol parameter test condition min. typ. max. unit 7.5.1 v 2 output voltage 5.0 v 7.5.2 v 2 output voltage tolerance active mode i load = 1ma ... 50ma, v s = 13.5v +/- 3 % 7.5.3 v hc1 output voltage tolerance active mode, high current i load = 50ma ... 100ma, v s = 13,5v +/- 4 % 7.5.4 v stb2 output voltage tolerance in low current mode i load = 0ua ...1ma v s = 13,5v +/- 5 % 7.5.5 v dp2 drop-out voltage i load = 25ma, v s = 5 v i load = 50ma, v s = 5 v 0,3 0.4 0,4 0.7 v v 7.5.6 i cc2 output current in active mode max. continuous load current 100 ma 7.5.7 i ccmax2 short circuit output current current limitation 200 300 500 ma 7.5.8 c load load capacitor ceramic (1) 1. placement close to the pad 0.22 f 7.5.9 v2 fail v2 fail threshold v2 forced 2 v L9952GXP electrical characteristics doc id 13518 rev 5 37/68 7.6 reset generator (v1 supervision) the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 5.25v < v s = 18v; t j = -40 to 130 c, unless otherwise specified. 7.7 watchdog 6v < v s < 18v; 4.8v < v1 < 5.2v; t j = -40 to 130 c, unless otherwise specified table 15. reset generator item symbol parameter test condition min. typ. max. unit 7.6.1 v rt1 reset threshold voltage1 v s, v v1 inc. / decreasing 4.5 4.63 4.75 v 7.6.2 v rt2 reset threshold voltage2 v s, v v1 inc. / decreasing 4.25 4.37 4.5 v 7.6.3 v reset reset pin low output voltage v1 > 1v, i reset = 1ma 0,2 0,4 v 7.6.4 r reset reset pull up int. resistor 60 110 204 k 7.6.5 t rr reset reaction time @iload = 1ma 6 40 s 7.6.6 v1 under-voltage filter time 16 s table 16. watchdog (1) 1. see figure 13 . item symbol parameter test condition min. typ. max. unit 7.7.1 t lw long open window 48,75 65 81,25 ms 7.7.2 t cw closed window 4.5 6 7.5 ms 7.7.3 t ow open window 7.5 10 12.5 ms 7.7.4 t wdr watchdog reset pulse time 1.5 2 2. 5 ms electrical characteristics L9952GXP 38/68 doc id 13518 rev 5 figure 13. watchdog timing t lw = long window < 65ms t cw = closed window < 6ms t ow = open window < 10ms trigger signal t wdr = watchdog reset = 2ms time / ms time / ms time / ms normal startup operation and timeout failures wd- trigger = correct trigger timing t lw t cw + t ow missing uc trigger signal t cw t cw + t ow nres- out t wdr t lw = early trigger timing = missing trigger t lw t wdr normal operation missing trigger early write t lw nres- out t wdr t wdr wd- trigger t lw t lw t wdr time / ms 0 0 L9952GXP electrical characteristics doc id 13518 rev 5 39/68 figure 14. watchdog, closed and open window tolerances and save trigger area 7.8 high side outputs 7.8.1 output (out_hs) the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; 4.8v < v1 < 5.2v; t j = -40c...130c, unless otherwise specified. 4.5 7.5 12 20 save trigger area tcw, min tcw, max twd= 10ms tow, max tow, min twd = nominal trigger time tcw = closed window tow = open window time / ms watchdog failure undefined undefined table 17. high side outputs (out_hs) item symbol parameter test condition min. typ. max. unit 7.8.1 r dson out_hs static drain source on-resistance to supply (iout_hs=150ma) tj = 25c 0 1.0 1.5 tj = 125c 01.63 7.8.2 td onhs switch on delay time 0.2 vs 10 35 60 s 7.8.3 td offhs switch off delay time 0.8vs 40 95 150 s 7.8.4 td sdhs short circuit filter time tested by scan chain 64* t osc 7.8.5 td arhs auto recovery filter time tested by scan chain 400* t osc 7.8.6 dvout/dt slew rate 0.2 0.5 0.8 v/s 7.8.7 i osdhs short circuit shutdown current 480 900 1320 ma 7.8.8 i old open load detection current 40 80 120 ma electrical characteristics L9952GXP 40/68 doc id 13518 rev 5 7.8.2 outputs (out1...4) the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; 4.8v < v1 < 5.2v; t j = -40c...130c, unless otherwise specified. 7.9 relay drivers the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; 4.8v < v1 < 5.2v; t j = -40 to 130 c, unless otherwise specified. table 18. high side outputs (out 1..4) item symbol parameter test condition min. typ. max. unit 7.8.11 r dson on ? resistance i load = 60ma @ tj=+25c 0712 7.8.12 i out short circuit shutdown current 8v < vs < 16v 140 235 330 ma 7.8.13 i old1 open load detection current 1 selectable via spi 0.8 2 4 ma 7.8.14 i old2 open load detection current 2 6813ma 7.8.15 sr slew rate 0.2 0.5 0.8 v/s 7.8.16 t donhs switch on delay time 0.2 v s 10 35 60 s 7.8.17 t doffhs switch off delay time 0.8 v s 40 95 150 s 7.8.18 t scf short circuit filter time tested by scan chain 64* t osc 7.8.19 i fw (1) 1. parameter guaranteed by design loss of gnd current (esd structure) 100 ma table 19. relay drivers item symbol parameter test condition min. typ. max. unit 7.9.1 r dson dc output resistance iload = 100ma @ tj = +25c 023 7.9.2 i out short circuit shutdown current 8v < vs < 16v 250 375 500 ma 7.9.3 v z output clamp voltage (1) i load = 100ma 40 48 v 7.9.4 t onhl turn on delay time to 10% v out 5 50 100 s 7.9.5 t offlh turn off delay time to 90% v out 5 50 100 s L9952GXP electrical characteristics doc id 13518 rev 5 41/68 7.10 wake up inputs ( wu1 .. wu4) the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; t j = -40 to 130 c, unless otherwise specified. 7.9.6 t scf short circuit filter time tested by scan chain 64* t osc 7.9.7 sr slew rate 0.2 2 4 v/s 1. the output is capable to switch off relay coils with the impedance of rl=160 ; l = 300mh (rl=220 ; l= 420mh); at v s = 40v (load dump condition) table 19. relay drivers (continued) item symbol parameter test condition min. typ. max. unit table 20. wake up inputs (1) (wu1...wu4) 1. defines whether the inputs w1..4 ar e configured with current source or current sink in standby mode. item symbol parameter test condition min. typ. max. unit 7.10.1 v wuthp wake-up negative edge threshold voltage 0.4 vs 0.45 vs 0.5 vs v 7.10.2 v wuthn wake-up positive edge threshold voltage 0.5 vs 0.55 vs 0.6 vs v 7.10.3 v hyst hysteresis 0.05 vs 0.1 vs 0.15 vs v 7.10.4 t wu minimum time for wake-up 51 64 77 s 7.10.5 i wu_stdby input current in standby mode 1.5v L9952GXP electrical characteristics doc id 13518 rev 5 43/68 7.12.7 v rxdhigh output voltage recessive level normal mode, v1=5v, 2ma 4.5 v 7.12.8 v thdom receiver threshold voltage recessive to dominant state 0.4 v s 0.45 v s 0.5 v s v 7.12.9 v threc receiver threshold voltage dominant to recessive state 0.5 v s 0.55 v s 0.6 v s v 7.12.10 v thhys receiver threshold hysteresis v threc - v thdom 0.07 v s 0.1 v s 0.175 v s v 7.12.11 v thcnt receiver tolerance center value (v threc + v thdom ) / 2 0.475 v s 0.5 v s 0.525 v s v 7.12.12 v thwkup receiver wakeup threshold voltage 1.0 1.5 2 v 7.12.13 v thwkdwn receiver wakeup threshold voltage 3.5 vs 2.5 vs 1.5 vs v 7.12.14 tbus dominant time for wakeup via bus sleep mode edge: rez.- dom. 64 s table 23. lin dc parameters item symbol parameter test condition min. typ. max. unit lin dc parameters 7.12.15 i lindomsc transmitter input current limit in dominant state v txd = v txdlow v lin = vbatmax = 18v 40 100 180 ma 7.12.16 i bus_pas_dom input leakage current at the receiver incl. pull-up resistor v txd = v txdhigh v lin = 0v , v bat =12v, slave mode -1 ma 7.12.17 i bus_pas_drec transmitter input current in recessive state v txd = v txdhigh 8v L9952GXP electrical characteristics doc id 13518 rev 5 45/68 7.12.27 d1 duty cycle 1 threc(max)=0.744*vs thdom(max)=0.581*vs vs= 7...18v, tbit= 50us, d1=tbus_rec(min)/(2xtbit) rbus, cbus: 1 k , 1 nf; 660 , 6.8 nf; 500 , 10 nf 0.396 - 7.12.28 d2 duty cycle 2 threc(min)=0.284*vs; thdom(min)=0.422*vs, vs= 7.6 ...18v, tbit= 50s, d1=tbus_rec(max)/(2xtbit) rbus, cbus: 1 k , 1 nf; 660 , 6.8 nf; 500 , 10 nf - 0.581 7.12.29 d3 duty cycle 3 threc(max)=0.778*vs; thdom(max)=0.616*v, vs= 7...18v tbit= 96s, d3 =tbus_rec(min)/(2xtbit) rbus, cbus: 1 k , 1 nf; 660 , 6.8 nf; 500 , 10 nf 0.417 - 7.12.30 d4 duty cycle 4 threc(min)=0.251*vs; thdom(min)=0.389*vs, vs= 7.6 ...18v, tbit= 96s d1 =tbus_rec(max)/(2xtbit) rbus, cbus: 1 k , 1 nf; 660 , 6.8 nf; 500 ,10 nf - 0.59 table 26. lin dc values item symbol parameter test condition min. typ. max. unit linpu dc values 7.12.31 r dson on resistance 10.5 16 7.12.32 i leak leakage current 1 ua table 25. lin timing (continued) item symbol parameter test condition min. typ. max. unit lin timing electrical characteristics L9952GXP 46/68 doc id 13518 rev 5 figure 15. lin transmit, receive timing tim e tim e v txd v lin v threc v t h dom 80% 20% tim e v rxd v lin dom v lin rec t txpdf t txpdr t rxpdf t r xpdr L9952GXP electrical characteristics doc id 13518 rev 5 47/68 7.13 operational amplifier the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; t j = -40...130c, unless otherwise specified. note: the operational amplifier is on-chip stabilized for external capacitive loads c l < 25pf (all operating conditions) table 27. operational amplifier item symbol parameter test condition min. typ. max. unit 7.13.1 gbw gbw product 1 3.5 7.0 mhz 7.13.2 avol dc dc open loop gain 80 db 7.13.3 psrr power supply rejection dc, vin =150 mv 80 db 7.13.4 v off input offset voltage -5 +5 mv 7.13.5 v icr common mode input range -0.2 0 3 v 7.13.6 v oh output voltage range high iload = 1ma to gnd 0.2 v s v s v 7.13.7 v ol output voltage range low iload = 1ma to v s 0 0.2 v 7.13.8 i lim+ output current limitation + dc 5 10 20 ma 7.13.9 i lim- output current limitation - dc -5 -10 -20 ma 7.13.10 sr+ slew rate positive 1 4 10 v/s 7.13.11 sr- slew rate negative -1 -4 -10 v/s electrical characteristics L9952GXP 48/68 doc id 13518 rev 5 7.14 spi 7.14.1 input: csn the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; 4.5v < v1 < 5.3v; all outputs open; t j = -40c...130c, unless otherwise specified. 7.14.2 inputs: clk, di, pwm 1, pwm 2 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v< v s < 18v; 4.5v < v1 < 5.3v; all outputs open; t j = -40c...130c, unless otherwise specified. table 28. spi (input csn) item symbol parameter test condition min. typ. max. unit 7.14.1 v csnlow input voltage low level active mode, v1 = 5v 0.5 1.0 1.6 v 7.14.2 v csnhigh input voltage high level active mode, v1=5v 1 1.75 2.5 v 7.14.3 v csnhys vcsnhigh - vcsnlow active mode, v1=5v 0.5 1.0 1.5 v 7.14.4 i csnpu csn pull up current active mode and v1 standby mode,v1=5v -5 -30 -60 a 7.14.5 i csnpd csn pull-down current in v bat - standby mode 53060a table 29. inputs: clk, di, pwm 1, pwm 2 item symbol parameter test condition min. typ. max. unit 7.14.6 t set delay time from standby to active mode switching from standby to active mode. time until output drivers are enabled after csn going to high. 160 300 s 7.14.7 v in l input low level v1 = 5 v 1.0 2.05 2.5 v 7.14.8 v in h input high level v1 = 5 v 1.5 2.8 3.3 v 7.14.9 v in hyst input hysteresis v1 = 5 v 0.4 0.75 1.5 v 7.14.10 i in pull down current at input v in = 1.5 v 5 30 60 a 7.14.11 c in (1) 1. value of input capacity is not measured in production test. para meter guaranteed by design. input capacitance at input csn, clk, di and pwm 1,2 0v < v1 < 5.3v 10 15 pf 7.14.12 f clk spi input frequency at clk 1mhz L9952GXP electrical characteristics doc id 13518 rev 5 49/68 7.14.3 input pwm 2 vth for flash mode the voltages are referred to ground. 6v < v s < 18v; 4.5v < v1 < 5.3v; all outputs open; t j = -40c...130c, unless otherwise specified. 7.14.4 di timing the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; 4.5v < v1 < 5.3v; all outputs open; t j = -40c...130c, unless otherwise specified. table 30. input pwm2 vth for flash mode item symbol parameter test condition min. typ. max. unit 7.14.13 v in l input low level (vin rising)) v1 = 5 v 6.1 7.25 8.4 v 7.14.14 v in h input high level (vin falling) v1 = 5 v 7.4 8.4 9.4 v 7.14.15 v in hyst input hysteresis v1 = 5 v 0.6 0.8 1.0 v table 31. di timing item symbol parameter test condition min. typ. max. unit 7.14.16 t clk clock period v1 = 5 v 1000 - ns 7.14.17 t clkh clock high time v1 = 5 v 400 - ns 7.14.18 t clkl clock low time v1 = 5 v 400 - ns 7.14.19 t set csn csn setup time, csn low before rising edge of clk v1 = 5 v 400 - ns 7.14.20 t set clk clk setup time, clk high before rising edge of csn v1 = 5 v 400 - ns 7.14.21 t set di di setup time v1 = 5 v 200 - ns 7.14.22 t hold di di hold time v1 = 5 v 200 - ns 7.14.23 t r_in rise time of input signal di, clk, csn v1 = 5 v - 100 ns 7.14.24 t f_in fall time of input signal di, clk, csn v1 = 5 v - 100 ns electrical characteristics L9952GXP 50/68 doc id 13518 rev 5 7.14.5 do, fso, dig_out3,4 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; 4.5v < v1 < 5.3v; all outputs open; t j = -40c...130c, unless otherwise specified. 7.14.6 do timing the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; 4.5v < v1 < 5.3v; all outputs open; t j = -40c...130c, unless otherwise specified. table 32. do, fso, digout3,4 item symbol parameter test condition min. typ. max. unit 7.14.25 v dol output low level v1 = 5 v, i d = -4ma 0.5 v 7.14.26 v doh output high level v = 5 v, i d = 4 ma 4.5 v 7.14.27 i dolk (1) 1. not valid for fso tristate leakage current v csn = v1, 0 v < v do L9952GXP electrical characteristics doc id 13518 rev 5 51/68 7.14.7 csn timing the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 18v; 4.5v < v1 < 5.3v; all outputs open; t j = -40c...130c, unless otherwise specified. figure 16. spi - input timing table 34. csn timing item symbol parameter test condition min. typ. max. unit 7.14.36 t csn_hi,min minimum csn hi time, active mode transfer of spi- command to input register 6- -s 0.8 vcc 0.8 vcc 0.8 vcc 0.2 vcc 0.2 vcc 0.2 vcc va l id valid csn clk di t set csn t clkh t se t clk t clkl t hold di t set di electrical characteristics L9952GXP 52/68 doc id 13518 rev 5 figure 17. spi - edges timing tf clk tr clk clk 0.8 vcc 0.5 vcc 0.2 vcc do (low to high 0.8 vcc 0.2 vcc tr do td do 0.8 vcc 0.2 vcc tf do do (high to low tf csn tr csn csn 0.8 vcc 0.5 vcc 0.2 vcc 50 % 50 % ten do_tri_l ten do_tri_h tdis do_l_tri tdis do_h_tri L9952GXP electrical characteristics doc id 13518 rev 5 53/68 figure 18. spi - csn low to high transition figure 19. spi - high to low transition csn don t 20% 80% t r in f in t off t doff t off state on state off state on state on t output current of a driver 50% 50% 80% 20% 20% 80% 50% output current of a driver c s n low to high: data f rom shi f tregister is transferred to output power switches t csn_hi,min csn clk di do csn high to lo w and clk sta y slo w :statusinfo r mation of data bit 0 (fault condition) is t r ansfe r ed to d o di: data is not accepted do: status information of data bit 0 (fault condition) will stay as long as csn is low time time time time 0 - spi control and status registers L9952GXP 54/68 doc id 13518 rev 5 8 spi control and status registers 8.1 spi registers 24bit shift register: first 2 bits are address (a1,a0) and 22 bits are data. during power-on reset, all registers are set to zero. note: during the shift in of the address bits, (2 clock periods) an internal error bit (err) is fed to the do output. d23,d22 -> error flags (seen from do) the error flag is generated by logic or combination of following error bits: vcc_fail1,2; tsd1,2; tw; ov,uw; oc_hs1..4; oc_ouths; oc_rel1..2; oc_v2 table 35. spi registers d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 a1 a0 data address [write] on5v2 on signals control register 0 go vcc go v bat trig on v21 on v20 rel 2 rel 1 out hs2 out hs1 out hs0 hs 42 hs 41 hs 40 hs 32 hs 31 hs 30 hs 22 hs 21 hs 20 hs 12 hs 11 hs 10 00 address [write] timer 2 timer 1 loop pullup / down wakeup sources ol wakeup sources control register 1 clr int_en t20 t13 t12 t11 t10 l2 l1 l0 u3 u2 u1 u0 w7 w6 w5 w4 w3 w2 w1 w0 01 address [write] input config reset level lin openload treshold control register 2 res i cmp ls ovuv lin slope ic 41 ic 40 ic 31 ic 30 ic 21 ic 20 ic 11 ic 10 lev 1 lev 0 txt tout linpu o_hs rec vlock out olt hs4 olt hs3 olt hs2 olt hs1 10 address [read] reserved wakeup wakeup input status overcurrent openload status register 0 res res cold start l i n i nh wu4 wu3 wu2 wu1 sht5 v2 rel2 oc rel1 oc hs oc hs4 oc hs3 oc hs2 oc hs1 oc hs ol hs4 ol hs3 ol hs2 ol hs1 ol err err address reserved lin state watchdog reset 5v restarts state status register 1 res res dom txd sht bat sht gnd trig wd 3 wd 2 wd 1 wd 0 r2 r1 r0 st1 st0 vcc 2 fail vcc 1 fail tsd 2 tsd 1 tw uv ov err err address L9952GXP spi control and status registers doc id 13518 rev 5 55/68 8.1.1 control register 0 while writing to the control register 0, the status register 0 can be read at the do-output of the spi. x table 36. control register 0 5v2 driver on signals bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 access w w w w w w w w w w w w w w w w w w w w w w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 name go v1 go v bat trig on v21 on v20 rel 2 rel 1 out hs2 out hs1 out hs0 hs 42 hs 41 hs 40 hs 32 hs 31 hs 30 hs 22 hs 21 hs 20 hs 12 hs 11 hs 10 table 37. configuration bit hsxx name / state definition/ function hsx2 hsx1 hsx0 defines the output confi guration of the high side drivers 1-4 table 38. configuration bit out_hsx name / state definition/ function out_hs 2 out_hs 1 out_hs 0 defines the output configuration of the high side driver out_hs 0 0 0 driver is off in all modes 0 0 1 driver is on in active mode, off in standby mode 010 driver is cyclic on with the timing of timer 1 in active mode and standby modes 011 driver is cyclic on with the timing of timer 2 in active mode and standby modes 1 0 0 driver is controlled by the pwm1 input 1 0 1 driver is controlled by the pwm2 input table 39. configuration bit relx name / state definition/ function relx defines the output configuration of the low side relay drivers 1/2 0 driver is off in all modes 1 driver is on in active mode (off in standby mode) table 40. configuration bit on_v2x name / state definition/ function on_v21 on_v20 defines in which modes the voltage regulator 2 is on 0 0 voltage regulator 2 is off in all modes spi control and status registers L9952GXP 56/68 doc id 13518 rev 5 8.1.2 control register 1 while writing to the control register 1, the status register 1 can be read at the do-output of the spi. 01 voltage regulator 2 is on in active mode; off in v 1 -standby, v bat -standby 10 voltage regulator 2 is on in active mode and v 1 standby; off in v bat -standby 1 1 voltage regulator 2 is on in all modes table 41. configuration bi t trig, go_vbat, go_v1 trig trigger bit for watchdog; inverted for each trigger event invert this bit for a proper watchdog trigger. go_vbat ?1? enters the v bat -standby mode. (dominant mode, if both standby modes are selected) go_v1 ?1? enters the v 1 -standby mode. table 40. configuration bit on_v2x (continued) name / state definition/ function table 42. control register 1 cyclic timer 1/2 loop pull up wakeup sources bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 access w w w w w w w w w w w w w w w w w w w w w w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 name clr int_en t20 t13 t12 t11 t10 l2 l1 l0 u3 u2 u1 u0 w7 w6 w5 w4 w3 w2 w1 w0 table 43. configuration bit wx name/state definition/function w7 w6 w5 w4 w3 w2 w1 w0 disables the corresponding wake up sources x x x x x x x 1 input wu1 is disabled as wake up source x x x x x x 1 x input wu2 is disabled as wake up source x x x x x 1 x x input wu3 is disabled as wake up source x x x x 1 x x x input wu4 is disabled as wake up source xxx1xxxx open load appearance / disappearance at out1 is disabled as wake up source xx1xxxxx open load appearance / disappearance at out2 is disabled as wake up source x1xxxxxx open load appearance / disappearance at out3 is disabled as wake up source L9952GXP spi control and status registers doc id 13518 rev 5 57/68 1xxxxxxx open load appearance / disappearance at out4 is disabled as wake up source 0 0 0 0 0 0 0 0 default: all wake up sources are enabled table 44. configuration bit ux name/state definition/function u3 u2 u1 u0 defines whether the inputs wu1..4 are configured with current source or current sink in standby mode. xxx1 input wu1 configured with a current source in standby mode (r wu_act pulldown resistor in active mode - see table 20. ) xx1x input wu2 configured with a current source in standby mode (r wu_act pulldown resistor in active mode - see table 20. ) x1xx input wu3 configured with a current source in standby mode (r wu_act pulldown resistor in active mode - see table 20. ) 1xxx input wu4 configured with a current source in standby mode (r wu_act pulldown resistor in active mode - see table 20. ) 0000 default: all inputs configured with a current sink in standby (r wu_act pulldown resistor in active mode - see table 20. ) table 45. configuration bit lx name/state defini tion/function l2 l1 l0 defines which signal is looped to the dig_out3 and dig_out4 (see note) dig_out3 dig_out4 0 0 0 wu3 (default) wu4 (default) 001 highz wu4 010 wu3 highz 0 1 1 wu3 open load hs2 1 0 0 open load hs1 wu4 1 0 1 open load hs1 open load hs2 1 1 0 open load hs1 highz 1 1 1 highz open load hs2 table 43. configuration bit wx (continued) name/state definition/function spi control and status registers L9952GXP 58/68 doc id 13518 rev 5 note: in v bat standby mode, digout 3 and digout4 are highz. table 46. configuration bit txx name/state defini tion/function t12 t11 t10 defines the period of the cyclic sense timer 1 which is selectable for out 1..4 and out_hs (see on signals control register 0) 0 0 0 period: 0.5 s 0 0 1 period: 1.0 s 0 1 0 period: 1.5 s 0 1 1 period: 2.0 s 1 0 0 period: 2.5 s 1 0 1 period: 3.0 s 1 1 0 period: 3.5 s 1 1 1 period: 4.0 s t13 defines the on time for the cyclic sense timer1 0 on time 10 ms 1 on time 20 ms t20 defines the on time of the cyclic sense timer 2 which is selectable for out 1..4 and ouths (see on signals control register 0) 0 period 50 ms / on time 100 us 1 period 50 ms / on time 1ms table 47. configuration bit int_enable name/state defini tion/function int_enable 0 interrupt mode disabled ( see section 2.7 ) 1 interrupt mode enabled clr clears the contents of st atus register 0 and 1 L9952GXP spi control and status registers doc id 13518 rev 5 59/68 8.1.3 control register 2 while writing to the control register 2, the status register 0 can be read at the do-output of the spi. table 48. control register 2 input filter configuration reset level lin open load threshold bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 access w w w w w w w w w w w w w w w w w w w w w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 name res i cmp lso vuv lin slope ic 41 ic 40 ic 31 ic 30 ic 21 ic 20 ic 11 ic 10 lev 1 lev 0 txdt out linp u o_hs rec vs lock out olt hs4 olt hs3 olt hs2 olt hs1 table 49. configuration bit olt_hsx, vslock out, o_hs_rec, linpu and txd_tout name/state definition/function olt_hsx open load threshold for the high side drivers out1..4 0: iopenload = 2ma; 1: iopenload = 8ma vslock out automatic recovery after vs over/under voltage ?0? (default): vs lockout is disabled, i.e. outputs will automatically recover (according to output settings in cr0) after vs over / under - voltage conditions has disappeared ?1?: vs lockout is enabled, i.e. outputs wi ll remain off after vs over / under voltage recovery conditions has disappeared, until the vs over / under voltage status bits (sr1, bit s0,1) are cleared by clr command (cr1, bit 21). o_hs_rec ?1? = recovery mode for out_hs driver. linpu ?1? will disable the master pull up linpu txd_tout ?1? will disable the dominant txd time-out for the lin interface. table 50. configuration bit levx name/state definition/function lev1 lev0 controls the reset level 0 0 set the reset threshold to 4.65v, typ. 0 1 set the reset threshold to 4.35v, typ. 1 x reserved (do not use for operation, set lev1 to ?0?) spi control and status registers L9952GXP 60/68 doc id 13518 rev 5 table 51. configuration bit icxx name/state definition/function ic(1..4)1 ic(1..4)0 selects the filter configuration for the wakeup inputs wu1 to 4 ic11 0 0 filter with 64 us filter time (static sense) ic21 0 1 enable filter after 80 us with a filter time of 16 us (cyclic sensing), timer2 ic31 1 0 enable filter after 800 us with a filter time of 16 us (cyclic sensing), timer2 ic41 1 1 enable filter after 800 us with a filter time of 16 us (cyclic sensing), timer1 table 52. configuration bit lin slope, ls_ovuv and icmp name/state definition/function lin slope change lin slope 0 high slew rate (default) 1 low slew rate ls_ovuv vs over / under voltage shutdown of rel1,2 (low side drivers) 0 enable (default): rel1,2 turned off in case of vs over/undervoltage 1 disable : rel1,2 remain on in case of vs over/undervoltage i cmp current supervision of v1 regulator in v 1 -standby mode. 0 enable (default) 1 disable res reserved L9952GXP spi control and status registers doc id 13518 rev 5 61/68 8.1.4 status register 0 the contents of the status register 0 can be read implicitly, while accessing the control register 0 or control register 2. table 53. status register 0 wakeup inputs over current open load bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 access r r r rrrrrr r r rrrrrrrrrrr reset 0 0 0 000000 0 0 00000000000 name res res cold start lin inh wu 4 wu 3 wu 2 wu 1 sht5v2 rel 2oc rel 1oc hs oc hs 4oc hs 3oc hs 2oc hs 10c hs o l hs 4ol hs 3ol hs 2ol hs 1ol table 54. configuration bit hsx_ol, hsx_oc and relx_oc name/state defini tion/function hs1..4_ol open load status from the high side driver out1..4. 0 no open load has been detected. 1 open load has been detected. hs_ol open load status from the high side driver out_hs 0 no open load has been detected. 1 open load has been detected. hs1..4_oc over current status fr om the high side driver out1..4. 0 no over current has been detected. 1 over current has been detected. hs_oc over current status from the high side driver out_hs. 0 no over current has been detected. 1 over current has been detected. rel 1,2_oc over current status from relais1,2 0 no over current has been detected. 1 over current has been detected. table 55. configuration bit sht5v2, wux, inh, lin and cold start name/state defini tion/function sht5v2 v2 short to ground at turn on; condition: v2 < 2v for more than 4ms. ?1? = fail wu4...wu1 status of the corresponding inputs wu1..4 (according to filter settings in cr2) spi control and status registers L9952GXP 62/68 doc id 13518 rev 5 note: res = reserved bits. 8.1.5 status register 1 the contents of the status register 1 can be read implicitly, while accessing the control register 1. inh wakeup initiated through inh source lin wakeup initiated through lin source cold start set to high when the internal power on reset occurs. will be cleared with the first spi access. table 55. configuration bit sht5v2, wux, inh, lin and cold start (continued) name/state defini tion/function table 56. status register 1 lin state wd resets 5v restarts state bit 2120191817161514131211109876543210 access r r r r r r r r r r r r r r r r r r r r r r reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 name res res dom txd sht bat sht gnd trig wd 3 wd 2 wd 1 wd 0 r2 r1 r0 st1 st0 v2 fail v1 fail tsd 2 tsd 1 tw uv ov table 57. configuration bit ov, uv, tw, tsdx and vx fail name definition, function ov over voltage failure of vs. uv under voltage failure of vs. tw temperature warning: the chip temperature exceeds 130c tsd1 thermal shutdown #1: the chip temperature exceeds 140c all outputs, except the voltage regulator 1 are switched off. tsd2 thermal shutdown #2: the chip temperature exceeds 155c all outputs, including the voltag e regulator 1 are switched off. v1 fail the output of voltage regulator 1 failed for at least 2s. conditions: (v1<2v for >2s) or (v1<2v at 4ms after turn-on). ?1?= fail v2 fail the output of voltage regulator 2 failed for at least 2s. conditions: (v2<2v for >2s) or (v2<2v at 4ms after turn-on). ?1?= fail table 58. configuration bit stx name mode st1 st0 0 0 active mode 0 1 v1-standby -> a readout is wake up condition -> active mode -> 00 is read L9952GXP spi control and status registers doc id 13518 rev 5 63/68 1 0 vbat-standby, a readout is not possible, as v1 is off 1 1 flash mode table 59. configuration bit rx, wdx, trig, sht_gnd, sht_bat and dom_txd name definiti on, function r2 r1 r0 number of unsuccessfully restarts after thermal shutdown wd3 wd2 wd1 wd0 number of watchdog time-outs (1) 1. bits are cleared at every valid wd trigger or when forced sleep mode is entered (after 15 wd failures have been detected) trig status of the trigger bit from control register 0 sht_gnd lin short to ground sht_bat lin short to battery dom_txd dominant txt res reserved table 58. configuration bit stx (continued) name mode package and packing information L9952GXP 64/68 doc id 13518 rev 5 9 package and packing information 9.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 9.2 powersso-36 pa ckage information figure 20. powersso-36 package dimensions table 60. powersso-36 mechanical data symbol millimeters min. typ. max. a- -2.45 a2 2.15 - 2.35 a1 0 - 0.1 b 0.18 - 0.36 c 0.23 - 0.32 L9952GXP package and packing information doc id 13518 rev 5 65/68 d 10.10 - 10.50 e7.4 - 7.6 e-0.5- e3 - 8.5 - f-2.3- g- -0.1 g1 - - 0.06 h 10.1 - 10.5 h- -0.4 k0-8 l 0.55 - 0.85 m-4.3- n - - 10 deg o-1.2- q-0.8- s-2.9- t - 3.65 - u-1.0- x4.1 - 4.7 y6.5 - 7.1 table 60. powersso-36 mechanical data (continued) symbol millimeters min. typ. max. package and packing information L9952GXP 66/68 doc id 13518 rev 5 9.3 powersso-36 packing information figure 21. powersso-36 tube shipment (no suffix) figure 22. powersso-36 tape and reel shipment (suffix ?tr?) all dimensions are in mm. base qty 49 bulk qty 1225 tube length (0.5) 532 a 3.5 b 13.8 c (0.1) 0.6 a c b base qty 1000 bulk qty 1000 a (max) 330 b (min) 1.5 c (0.2) 13 f 20.2 g (+2 / -0) 24.4 n (min) 100 t (max) 30.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 (0.1) 4 component spacing p 12 hole diameter d (0.05) 1.55 hole diameter d1 (min) 1.5 hole position f (0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 (0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets sealed with cover tape. user direction of feed L9952GXP revision history doc id 13518 rev 5 67/68 10 revision history table 61. document revision history date revision changes 24-aug-2007 1 initial release. 07-sep-2007 2 table 18: high side outputs (out 1..4) : modified openload detection current 1 parameter value (item 7.8.13). table 20: wake up inputs(wu1...wu4) : modified input current in standby mode test condition (item 7.10.5). table 22: lin receiver : modified symmetry of transmitter propagation delay time parameter value (item 7.12.24). added section 9.3: powersso-36 packing information . 21-sep-2007 3 section 7.2: oscillator : changed vs minimum value from 7 to 6 v. table 10: supply and supply monitoring : ? changed parameter 7.1.10 (i v(batwu) ) max value from 300 to 320 a ? changed parameter 7.1.11 (i v(batwu) ) max value from 380 to 410 a. 11-apr-2008 4 modified figure 4.: watchdog modified section 2.13: low side driver outputs rel1, rel2 . added note to section 2.2.2 : flash mode . section table 48.: control register 2 : changed definition to v s lock out parameter. added section 6.3: package and pcb thermal data . modified section 7.14.3: input pwm 2 vth for flash mode . table 42: control register 1 : modified "pull down" settings for the wake- up inputs wu1..4 . 08-jul-2009 5 table 60: powersso-36 mechanical data : ? deleted a (min) value ? changed a (max) value from 2.47 to 2.45 ? changed a2 (max) value from 2.40 to 2.35 ? changed a1 (max) value from 0.075 to 0.1 ? added k row ? changed g (max) value from 0.075 to 0.1 L9952GXP 68/68 doc id 13518 rev 5 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military , air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 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